The invention relates to postage meters, and in particular, to electronic postage meters having microcomputer control of printing and accounting functions.
Devices of this type are generally known, and are discussed for example in U.S. Pat. No. 3,978,457. This patent discloses a system for a postage meter which includes a keyboard for the manual introduction of data corresponding to the postage to be printed in a Random Access Memory for real time operation. Data is stored in a nonvolatile memory upon power down and read into the Random Access Memory upon power up.
U.S. Pat. No. 4,481,604 describes an electronic postage meter having a redundant memory system in which for each postal printing operation, identical data is stored, respectively, in two separate, but identical CMOS battery backed non-volatile memories.
In these known devices, there have been found to be times when essential data has not properly been stored in the non-volatile memory of the meter. It has been found that one reason might be the improper selection of access to a particular device.
In known electronic postage meters, the microprocessor high order address bits or combination thereof are utilized in a standard decoder for selecting or enabling a particular memory or peripheral device to be accessed in accordance with the microcomputer instructions. While this normally works well, in many cases of improper operation of the microcomputer or failure of one of the address lines of the bus, an improper bit may be decoded and the select logic gate which then enables the wrong device may cause wrong data to be read from memory or in the worst case cause data to be written into an unknown memory or peripheral with no indication of any malfunction. When this happens there is a strong possibility of service personnel not being able to recover essential information from the non-volatile memory in the postage meter when the postage meter fails. In U.S. Pat. No. 4,901,273, in order to assure that data is written only to the appropriate non-volatile memory, a logic circuit has been provided which will decode the addresses called by the microprocessor in such manner as to ensure the selection of the appropriate memory or device, and particularly the NVM, only when the addresses, appropriate to that device, are communicated.
U.S. Pat. No. 4,998,203 describes a memory protection circuit which, among other things, locks the NVM during a write-cycle should the NVM remain write enabled for too long, approximately 16 clock cycles, which indicates a high order fault condition.
It has been found that to further protect the NVM, memory protection can be further enhanced by time controlling the control flip-flops of the decoder system described in U.S. Pat. No. 4,901,273. That is, during the write cycle of the system microcontroller, a non-fatal software error may occur, wherein a decoder timer unlocks the control flip-flop at the beginning of the write cycle and relocks the control flip-flops after a specified amount of time to allow the microcontroller to overcome the soft error condition, such as by a retry. In contrast to the hard fault timer, the system is not locked.